1. Field of the Invention
This invention relates to queuing systems, and in particular to an enhanced performance First In First Out (FIFO) queuing system having minimal implementation logic and polling requirements.
2. Description of the Related Art
It is a problem in the field of high-performance low-cost graphics accelerator circuits used in three-dimensional imaging devices, to implement an efficient, high-performance queuing system requiring minimal circuit implementation space and minimal status polling requirements. The need to implement smaller and more efficient queuing systems in graphics accelerator circuits, as well as in other electronic devices, is a result of products being designed to provide maximum processing performance and efficiency in increasingly limited circuit space environments.
A traditional FIFO queuing system has at least one electronic device, component, and/or process, generically called device "A", that writes to a FIFO queue, and at least one other electronic device, component, and/or process, generically called device "B", that reads from the same FIFO queue. It is useful for device A to know if space is available to write to the FIFO queue, and for device B to know if data is available to read from the FIFO queue. Traditional FIFO queuing systems resolve the space/data availability issue by requiring that device A poll a FIFO queue controller prior to each write operation to determine if space is available to write to the FIFO queue. If the FIFO queue controller responds with a "full" indication, then device A must wait and repeatedly poll the FIFO queue controller until it is determined that space is available to write to the FIFO queue. In the mean time, device A is unable to perform additional processing until the present processing result is written to the FIFO queue.
Similarly, device B is required to poll the FIFO queue controller prior to each read operation to determine if data is available to read from the FIFO queue. If the FIFO queue controller responds with an "empty" indication, then B must wait and repeatedly poll the FIFO queue controller until data is available to read from the FIFO queue. In the mean time, device B is unable to perform additional processing until new data is available from the FIFO queue. However, the seemingly simple logic required to implement a traditional FIFO queuing system such as the one described above, is too large, and the repeated status polling prior to each read/write operation too costly, for use by FIFO queuing systems implemented in high-performance electronic devices having limited circuit space and no tolerance for status polling that wastes processing time.
For these reasons, traditional FIFO queuing systems fail to meet the circuit implementation space requirements and processing performance requirements of high-performance electronic devices such as the graphics accelerator circuits used in three-dimensional imaging devices. The need for an efficient high-performance FIFO queuing system has heretofore not been satisfied.